Date of Award

5-2024

Document Type

Thesis

Degree Name

Master of Science (MS)

Department

Electrical and Computer Engineering (Holcomb Dept. of)

Committee Chair/Advisor

Jon C Calhoun

Committee Member

Yingie Lao

Committee Member

Tao Wei

Abstract

In HPC, the ability to generate data is outpacing our hardware capabilities of storing said data. This presents the need for compression so we can keep important data preserved without costly hardware upgrades or worrying about hardware speed limitations. Traditional forms of compression are software based, which presents a speed issue that can lead to bottlenecks when storing data.Scientific data lossy compression methods such as SZ enable a speedup on memory transfer by simplifying computation to minimize the essential data size. SZx is a lightweight version of the popular SZ floating point compressor that may benefit from hardware acceleration. This paper introduces MARY (Micro Architecture for Reduced Yield), a hardware-based compressor that addresses a gap in lossy data compression which is currently largely software-based. The base algorithm used in MARY is based on SZx, a fast software-based lossy compression technique. However, unlike software-based compression techniques, MARY is a bare metal architecture that utilizes the added speed and efficiency of hardware-based compression. We introduce MARY, a hardware-based compressor that is designed to be highly efficient and effective by implementing the SZx core functionality on an FPGA. We describe the architecture of the design, how it is optimized for lossy compression, and provide a detailed explanation of how MARY utilizes the base algorithm from SZx on bare metal to achieve fast compression times while minimizing data loss. To evaluate the effectiveness of MARY, we compare it to other state-of-the-art compression techniques. We demonstrate that MARY can outperform these techniques in terms of speed if given the correct optimizations, making it well-suited for use in a scientific data environment.

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